Design of Robust, Ultra Low-Power Efficient Full Adder Cell in sub-45nm Technologies

Nowadays, there is a need to design microelectronic circuits which utilizes less energy and small area because of extensive growth of portable devices like laptops, digital watches and personal communication devices like mobile phones, and continuous shrinking of technology node. Many applications require circuits of high throughput, small area and consume ultra-low power. In this regard, this paper brings forward a novel full adder circuit that uses 10-Transistors and improved version of the proposed circuit. This full adder uses low power XOR gates to generate sum signal and a multiplexer of two transistors, to generate carry out signal. Generic Process Design Kit (GPDK) 45nm technology is employed in Cadence virtuoso design environment to design circuits which are simulated with Spectre simulator.